1. Field of the Invention
The invention relates to an integrated current-injection logic circuit comprising transistors whose bases are connected to current injectors and to a collector of at least one further transistor, said integrated circuit being formed by a plurality of elementary cells which are arranged in series across a power supply, in such a way that the cells form superimposed stages between which the supply voltage is distributed, a first stage and a second stage at a lower level being logically interconnected by means of an interface device in which the collector of a first transistor, which supplies the signal, controls a first auxiliary transistor whose conductivity type is opposite to that of said first transistor and whose collector is connected to that base of a second transistor in the second stage which is not connected to a current injector.
2. Description of the Prior Art
In the literature one type of injection logic is known by the name of I.sup.2 L circuit (see for example French Pat. No. 2,244,262). It has the double advantage of a low power dissipation (smaller than 1 p J/gate) and a high integration density which approximates that of MOS (several hundreds of gates per mm.sup.2), thus permitting its use in LSI and VLSI logic circuits. However, the interface device mentioned in the opening paragraph has the disadvantage that it has a very low switching speed. When the current injected into the base of the second transistor by the auxiliary transistor is interrupted, the second transistor switches from the saturated state (0.1 volt between collector and emitter, which corresponds to logic 0) to the cutoff state (0.7 volt between the collector and emitter, which is equivalent to logic 1). However, this switching operation is delayed by the slow elimination through recombination of charges stored in the base zone of the second transistor. French Patent Specification Nos. 2,323,234 and 2,354,634 describe substantially identical interface devices, whose operation is based on the principle of rapidly draining said stored charges via a third transistor, which is controlled by a second auxiliary transistor which is of the same conductivity type as the first one and which conducts when the first one is cut off. However, for controlling such devices an additional fourth transistor and two current injectors are required.